With the development of display technology, liquid crystal display (LCD) and other flat panel display devices with advantages of high quality, low power consumption, thin body and broad application are widely used in mobile phones, television, personal digital assistant, digital cameras, notebook, desktop and other consumer electronic products, becoming a mainstream in the display device.
In general, a liquid crystal display panel is composed of a color filter substrate (CF), a thin film transistor substrate (TFT), a liquid crystal (LC) and a sealant sandwiched between the color filter substrate and a thin film transistor substrate. The molding process of the liquid crystal display panel includes: front-end array process (thin film, photolithography, etching and stripping), middle-end cell process (TFT substrate and CF substrate bonding), and back-end assembling process (driving IC and printed circuit board lamination). Wherein, the front-end array process is mainly forming the TFT substrate to control the movement of liquid crystal molecules; the middle-end cell process is mainly adding liquid crystal between the TFT substrate and the CF substrate; and the back-end process is mainly laminating the driving IC and integrating to the printed circuit board, so as to rotate the liquid crystal molecules to display images.
Array test circuit is used for testing electrical situation on array substrate during the array process of the liquid crystal display panel, it plays a very important role for improving product yield. As shown in FIGS. 1 and 2, the array test circuit is typically located in the upper part of the panel display area, comprising: a plurality of driving units, each driving units comprising: a plurality of array test pads 100, a demultiplexer circuit (DEMUX) 200 that electrically connected to the plurality of array test pads 100, and a test-enable circuit 300. Wherein the demultiplexer circuit 200 includes: one first demultiplexer module 201 and four second demultiplexer module 202; the first demultiplexer module 201 comprises four first thin film transistors (T1), each second demultiplexer modules 202 comprises six second thin film transistors (T2), the test-enable circuit 300 includes twenty-four third thin film transistors (T3).
The gates of the four first thin film transistors (T1) are electrically connected to a first, a second, a third and a fourth control signals (ATC1˜ATC4), respectively; the sources of the four first thin film transistors (T1) are all accessed to the data signal; and the drains of the four first thin film transistors (T1) are electrically connected to a corresponding second demultiplexer module 202, respectively.
The gates of the six second thin film transistor (T2) are electrically connected to a fifth, a sixth, a seventh, an eighth, a ninth, and a tenth control signals (ATC5˜ATC10); the sources of the six second thin film transistors (T2) are electrically connected to the drains of the first thin film transistor (T1) corresponding to the second demultiplexer module 202 thereof, the drains of the six second thin film transistors (T2) are electrically connected to the test-enable circuit 300.
The gates of the twenty-four third thin film transistors (T3) are all accessed to the enable signal (ATEN), the sources of the twenty-fourth third thin film transistor (T3) are electrically connected to the drains of a second thin film transistor (T2), respectively, and the drains of the twenty-four third thin film transistor (T3) are electrically connected to one data line, respectively.
As shown in FIG. 2, the first to the tenth control signals (ATC1˜ATC10), the test-enable signal (ATEN), and the data signal are all input to the corresponding thin film transistors via corresponding array test pads 100 when the array is tested. However, after the test is completed, in a normal operation state of the panel, the array test pads are no longer having signal input, the circuit does not work, the first to the tenth control signals (ATC1˜ATC10) are in the floating state, causing each thin film transistor of the demultiplexer 100 also in a floating state, resulting in the panel in an unknown state, causing uncertainty and affecting the stability of the display panel.